Lowest cost, lowest component count switcher solution? Cost competitive with linears above 5W? Built-in Auto-restart and Current limiting? Latching Thermal shutdown for system level protection?

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Lowest cost, lowest component count switcher solution? Cost competitive with linears above 5W? Built-in Auto-restart and Current limiting? Latching Thermal shutdown for system level protection? Implements Flyback, Forward, Boost or Buck topology? Works with primary or opto feedback? Stable in discontinuous or continuous conduction mode?

Source connected tab for low EMI? This brings TOPSwitch technology advantages to many new applications, i. TV, Monitor, Audio amplifiers, etc. Typical Flyback Application. The internal lead frame of this package uses six of its pins to transfer heat from the chip directly to the board, eliminating the cost of a heat sink. Package outline: Y03A 2. Assumes appropriate heat sinking to keep the maximum TOPSwitch junction temperature below ?

Soldered to 1 sq. P is the maximum practical continuous power output level for conditions shown. The continuous power capability MAX in a given application depends on thermal environment, transformer design, efficiency required, minimum specified input voltage, input storage capacitance, etc.

Functional Block Diagram. Provides internal bias current during start-up operation via an internal switched highvoltage current source. Internal current sense point. Internal shunt regulator connection to provide internal bias current during normal operation. Primary side circuit common and reference point.

P and G package — Primary side control circuit common and reference point. Pin Configuration. High efficiency is achieved through the use of CMOS and integration of the maximum number of functions possible. CMOS process significantly reduces bias currents as compared to bipolar or discrete solutions. Refer to Figure 2 for a block diagram and to Figure 6 for timing and voltage waveforms of the TOPSwitch integrated circuit.

Start-up Waveforms for a Normal Operation and b Auto-restart. The total amount of capacitance connected to this pin CT also sets the autorestart timing as well as control loop compensation. V is C regulated in either of two modes of operation.

Hysteretic regulation is used for initial start-up and overload operation. Shunt regulation is used to separate the duty cycle error signal from the control circuit supply current. The current source provides sufficient current to supply the control circuitry as well as charge the total external capacitance CT.

The first time VC reaches the upper threshold, the high-voltage current source is turned off and the PWM modulator and output transistor are activated, as shown in Figure 5 a. During normal operation when the output voltage is regulated feedback control current supplies the VC supply current. The shunt regulator keeps VC at typically 5. The low E dynamic impedance of this pin ZC sets the gain of the error amplifier when used in a primary feedback configuration.

The dynamic impedance of the CONTROL pin together with the external resistance and capacitance determines the control loop compensation of the power system. Oscillator The internal oscillator linearly charges and discharges the internal capacitance between two voltage levels to create a sawtooth waveform for the pulse width modulator. The nominal frequency of kHz was chosen to minimize EMI and maximize efficiency in power supply applications.

Trimming of the current reference improves oscillator frequency accuracy. The error signal E across RE is filtered by an RC network with a typical corner frequency of 7 kHz to reduce the effect of switching noise. The filtered error signal is compared with the internal oscillator sawtooth waveform to generate the duty cycle waveform.

As the control current increases, the duty cycle decreases. The maximum duty cycle is set by the symmetry of the internal oscillator. The high-voltage current source turns on and charges the external capacitance again. Charging current is shown with a negative polarity and discharging current is shown with a positive polarity in Figure 6.

The hysteretic auto-restart comparator keeps VC within a window of typically 4. The auto-restart circuit has a divide-by-8 counter which prevents the output MOSFET from turning on again until eight discharge-charge cycles have elapsed. Autorestart continues to cycle until output voltage regulation is again achieved. Bandgap Reference All critical TOPSwitch internal voltages are derived from a temperature-compensated bandgap reference. This reference is also used to generate a temperature-compensated current source which is trimmed to accurately set the oscillator frequency Gate Driver The gate driver is designed to turn the output MOSFET on at a controlled rate to minimize common-mode EMI.

The gate drive current is trimmed for improved accuracy. Error Amplifier The shunt regulator can also perform the function of an error amplifier in primary feedback applications. The shunt regulator voltage is accurately derived from the temperature compensated bandgap reference. VC reset IC 0 12 81??? The leading edge blanking circuit inhibits the current limit comparator for a short time after the output MOSFET is turned on. The leading edge blanking time has been set so that current spikes caused by primary-side capacitances and secondary-side rectifier reverse recovery time will not cause premature termination of the switching pulse.

The current limit can be lower for a short period after the leading edge blanking time as shown in Figure To avoid triggering the current limit in normal operation, the drain current waveform should stay within the envelope shown. V regulation changes from C shunt mode to the hysteretic auto-restart mode described above. When the fault condition is removed, the power supply output becomes regulated, VC regulation returns to shunt mode, and normal operation of the power supply resumes.

Activating the power-up reset circuit by removing and restoring input power or momentarily pulling the CONTROL pin below the power-up reset threshold resets the latch and allows TOPSwitch to resume normal power supply operation. VC is regulated in hysteretic mode and a 4. Hysteretic operation occurs during auto-restart and overtemperature latched shutdown.

F 10V VR1 C3 ? F 10V R2 ? D3 IN R1 10? C4 ? F 16V C5 47? Refer to the Data Book and Design Guide for additional examples. This supply is used in appliances where certain stand-by functions e. The 5V secondary is used to supply the stand-by function and the 12V non-isolated output is used to supply power for the PWM controller of the main power supply and other primary side functions. For this application the input rectifiers and input filter are sized for the main supply and are not shown.

The TOP is packaged in a 8 pin power dip package. The output voltage 5V is directly sensed by the zener diode VR1 and the optocoupler U2.

The output voltage is determined by the sum of the zener voltage and the voltage drop across the LED of the optocoupler the voltage drop across R1 is negligible. C5 47? H C3 ? F 35 V D3 1N C4 0. F T1 R1 ? U2 PCA R2 ? This low cost package transfers heat directly to the board through six source pins, eliminating the heatsink and the associated cost.

Output voltage is directly sensed by optocoupler U2 and Zener diode VR2. Other output voltages are possible by adjusting the transformer turns ratio and value of Zener diode VR2. D1 and VR1 clamp leading-edge voltage spikes caused by transformer leakage inductance. The power secondary winding is rectified and filtered by D2, C2, L1, and C3 to create the 12V output voltage. R2 and VR2 provide a slight pre-load on the 12V output to improve load regulation at light loads.

L2 and Y1-safety capacitor C7 attenuate common mode emission currents caused by high voltage switching waveforms on the DRAIN side of the primary winding and the primary to secondary capacitance.

Leakage inductance of L2 with C1 and C6 attenuates differential-mode emission currents caused by the fundamental and harmonics of the trapezoidal or triangular primary current waveform. The maximum recommended clamp Zener voltage for the TOP2XX series is V and the corresponding maximum reflected output voltage on the primary is V. The transformer should be designed such that the rate of change of drain current due to transformer saturation is within the absolute maximum specification?

ID in ns before turn off as shown in Figure As a guideline, for most common transformer cores, this can be achieved by maintaining the Peak Flux Density at maximum I limit current below Gauss mT. The transformer spreadsheets Rev. To avoid this problem when doing bench evaluations, it is recommended that the VC power supply be turned on before the DRAIN voltage is applied. This is because the input energy storage capacitors are not completely discharged and the CONTROL pin capacitance has not discharged below the internal power-up reset voltage.

In some cases, minimum loading may be necessary to keep a lightly loaded or unloaded output voltage within the desired range due to the minimum ON-time. Therefore, the original TOPSwitch design must be reviewed to make sure that the selected TOPSwitch-II replacement device and other primary components are not over stressed under abnormal conditions.


Power Integrations Inc

All the products will packing in anti-staticbag. Ship with ESD antistatic protection. We will inspect all the goods before shipment,ensure all the products at good condition and ensure the parts are new originalmatch datasheet. After all the goods are ensure no problems afterpacking, we will packing safely and send by global express. It exhibitsexcellent puncture and tear resistance along with good seal integrity.


Power Integrations Inc



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