These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0. The output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
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These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling.
The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0. The output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground.
All Rights Reserved All other trademarks mentioned are the property of their respective owners. They are not intended for use in Reflow solder processing applications. Indefinite Operating Conditions Temperature Range. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. See Tech Brief TB for details 2. Short circuit may be applied to ground or to either supply.
Two class A amplifier stages provide the voltage gain, and a unique class AB amplifier stage provides the current gain necessary to drive low-impedance loads. A biasing circuit provides control of cascoded constant current flow circuits in the first and second stages.
The CA includes an on chip phase compensating capacitor that is sufficient for the unity gain voltage follower configuration. When the CA is operating such that output Terminal 6 is sinking current to the V- bus, transistor Q16 is the current sinking element.
Transistor Q20, in turn, is biased by current flow through R13, zener D8, and R The dynamic current sink is controlled by voltage level sensing. When output current sinking mode operation is required, the collector potential of transistor Q13 is driven below its quiescent level, thereby causing Q17, Q18 to decrease the output voltage at Terminal 6. As a consequence, there is an incremental increase in current flow through Q20, R12, Q21, D6, R7, and the base of Q As a result, Q16 sinks current from Terminal 6 in direct response to the incremental change in output voltage caused by Q This sink current flows regardless of load; any excess current is internally supplied by the emitter-follower Q Short circuit protection of the output circuit is provided by Q19, which is driven into conduction by the high voltage drop developed across R11 under output short circuit conditions.
Under these conditions, the collector of Q19 diverts current from Q4 so as to reduce the base current drive from Q17, thereby limiting current flow in Q18 to the short circuited load terminal. Input Stage The schematic diagram consists of a differential input stage using PMOS field-effect transistors Q9, Q10 working into a mirror pair of bipolar transistors Q11, Q12 functioning as load resistors together with resistors R2 through R5. The mirror pair transistors also function as a differential-to-single-ended converter to provide base current drive to the second stage bipolar transistor Q Cascode-connected bipolar transistors Q2, Q5 are the constant current source for the input stage.
The base biasing circuit for the constant current source is described subsequently. The small diodes D3, D4, D5 provide gate oxide protection against high voltage transients, e. Bias Circuit Quiescent current in all stages except the dynamic current sink of the CA is dependent upon bias current flow in R1. The function of the bias circuit is to establish and maintain constant current flow through D1, Q6, Q8 and D2.
D1 is a diode connected transistor mirror connected in parallel with the base emitter junctions of Q1, Q2, and Q3. D1 may be considered as a current sampling diode that senses the emitter current of Q6 and automatically adjusts the base current of Q6 via Q1 to maintain a constant current through Q6, Q8, D2.
The base currents in Q2, Q3 are also determined by constant current flow D1. Furthermore, current in diode connected transistor Q2 establishes the currents in transistors Q14 and Q Second Stage Most of the voltage gain in the CA is provided by the second amplifier stage, consisting of bipolar transistor Q13 and its cascode connected load resistance provided by bipolar transistors Q3, Q4.
On-chip phase compensation, sufficient for a majority of the applications is provided by C1. Additional Miller-Effect compensation roll off can be accomplished, when desired, by simply connecting a small capacitor between Terminals 1 and 8. Terminal 8 is also used to strobe the output stage into quiescence. When terminal 8 is tied to the negative supply rail Terminal 4 by mechanical or electrical means, the output Terminal 6 swings low, i.
Typical Applications Wide dynamic range of input and output characteristics with the most desirable high input impedance characteristics is achieved in the CA by the use of an unique design based upon the PMOS Bipolar process. Input common mode voltage range and output swing capabilities are complementary, allowing operation with the single supply down to 4V.
The wide dynamic range of these parameters also means that this device is suitable for many single supply applications, such as, for example, where one input is driven below the potential of Terminal 4 and the phase sense of the output signal must be maintained — a most important consideration in comparator applications.
Output Stage The CA Series circuits employ a broad band output stage that can sink loads to the negative supply to complement the capability of the PMOS input stage when operating near the negative rail. Under these conditions, the collector potential of Q13 is sufficiently high to permit the necessary flow of base current to emitter follower Q17 which, in turn, drives Q This connection assures that the maximum output signal swing will not go more positive than the zener voltage minus two base-to-emitter voltage drops within the CA These voltages are independent of the operating supply voltage.
Figure 4 shows some typical configurations. Note that a series resistor, RL, is used in both cases to limit the drive available to the driven device. Moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit.
This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized.
Typical values of series resistors R that may be placed at either end of the potentiometer, see Figure 3B, to optimize its utilization range are given in the Electrical Specifications table.
An alternate system is shown in Figure 3C. This circuit uses only one additional resistor of approximately the value shown in the table. A current regulator based upon the PMOS threshold voltage maintains reasonable constant operating current and hence consistent performance down to these lower voltages.
This limit is reached at a total supply voltage just below 4V. The output voltage range also begins to extend down to the negative supply rail, but is slightly higher than that of the input. Figure 8 shows these characteristics and shows that with 2V dual supplies, the lower extreme of the input common mode voltage range is below ground potential. The slew rate will, however, also be proportionally reduced by using this additional capacitor.
Figure 5 shows the typical settling time required to reach 1mV or 10mV of the final value for various levels of large signal inputs for the voltage follower and inverting unity gain amplifiers. Input Circuit Considerations As mentioned previously, the amplifier inputs can be driven below the Terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry.
Moreover, some current limiting resistance should be provided between the inverting input and the output when FN This resistance prevents the possibility of extremely large input signal transients from forcing a signal through the input protection network and directly driving the internal constant current source which could result in positive feedback via the output terminal. The typical input current is on the order of 10pA when the inputs are centered at nominal device dissipation.
As the output supplies load current, device dissipation will increase, raising the chip temperature and resulting in increased input current.
Figure 7 shows typical input terminal current versus ambient temperature for the CA Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite polarity reverse the offset. Figure 9 shows the typical offset voltage change as a function of various stress voltages at the maximum rating of oC for metal can ; at lower temperatures metal can and plastic , for example, at 85oC, this change in voltage is considerably less.
In typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage.
Analog frequency readout is readily accomplished by the means described above because the output current of the CAA varies approximately one decade for each 60mV change in the applied voltage, VABC voltage between Terminals 5 and 4 of the CAA of the function generator.
Now, only the reference voltage must be established to set the lower limit on the meter. The three remaining transistors from the CA Array used in the sweep generator are used for this reference voltage.
In addition, this reference generator arrangement tends to track ambient temperature variations, and thus compensates for the effects of the normal negative temperature coefficient of the CAA VABC terminal voltage. Another output voltage from the reference generator is used to insure temperature tracking of the lower end of the Frequency Adjustment Potentiometer. A large series resistance simulates a current source, assuring similar temperature coefficients at both ends of the Frequency Adjustment Control.
To calibrate this circuit, set the Frequency Adjustment Potentiometer at its low end. Then adjust the Minimum Frequency Calibration Control for the lowest frequency. To establish the upper frequency limit, set the Frequency Adjustment Potentiometer to its upper end and then adjust the Maximum Frequency Calibration Control for the maximum frequency. Because there is interaction among these controls, repetition of the adjustment procedure may be necessary. Two adjustments are used for the meter.
The meter sensitivity control sets the meter scale width of each decade, while the meter position control adjusts the pointer on the scale with negligible effect on the sensitivity adjustment. The CA functions as a noninverting readout amplifier of the triangular signal developed across the integrating capacitor network connected to the output of the CAA current source.
Buffered triangular output signals are then applied to a second CA functioning as a high speed hysteresis switch. Output from the switch is returned directly back to the input of the CAA current source, thereby, completing the positive feedback loop The triangular output level is determined by the four 1N level limiting diodes of the second CA and the resistor divider network connected to Terminal No.
These diodes establish the input trip level to this switching stage and, therefore, indirectly determine the amplitude of the output triangle. Compensation for propagation delays around the entire loop is provided by one adjustment on the input of the CA This adjustment, which provides for a constant generator amplitude output, is most easily made while the generator is sweeping. High frequency ramp linearity is adjusted by the single 7pF to 60pF capacitor in the output of the CAA.
It must be emphasized that only the CAA is characterized for maximum output linearity in the current generator function.
Two break points are established by diodes D1 through D4. Positive feedback via D5 and D6 establishes the zero slope at the maximum and minimum levels of the sine wave.
This technique is necessary because the voltage follower configuration approaches unity gain rather than the zero gain required to shape the sine wave at the two extremes. Low driving impedance is required of the CAA current source to assure smooth operation of the Frequency Adjustment Control.
This low-driving impedance requirement is easily met by using a CA connected as a voltage follower. Moreover, a meter may be 10 FN This asymmetry is due to slightly different positive and negative integration from the CAA and from the PC board and component leakages at the pA level. The initial slope is adjusted with the potentiometer R1, followed by an adjustment of R2.
The final slope is established by adjusting R3, thereby adding additional segments that are contributed by these diodes. Because there is some interaction among these controls, repetition of the adjustment procedure may be necessary.